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for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v dd1 v dd2 sclk din sstrb cs dout gnd refadj top view max1282/ max1283 tssop ch0 ch1 com ch2 ch3 shdn ref 19-1688; rev 0; 5/00 typical operating circuit appears at end of data sheet. pin configuration ordering information spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. general description the max1282/max1283 12-bit analog-to-digital convert- ers (adcs) combine a 4-channel analog-input multiplexer, high-bandwidth track/hold (t/h), and serial interface with high conversion speed and low power consumption. the max1282 operates from a single +4.5v to +5.5v supply; the max1283 operates from a single +2.7v to +3.6v sup- ply. both devices?analog inputs are software configurable for unipolar/bipolar and single-ended/pseudo-differential operation. the 4-wire serial interface connects directly to spi/qspi/microwire devices without external logic. a serial strobe output allows direct connection to tms320-family digital signal processors. the max1282/ max1283 use an external serial-interface clock to perform successive-approximation analog-to-digital conversions. the devices feature an internal +2.5v reference and a ref- erence-buffer amplifier with a ?.5% voltage-adjustment range. an external reference with a 1v to v dd range may also be used. the max1282/max1283 provide a hardwired shdn pin and four software-selectable power modes (normal opera- tion, reduced power (redp), fast power-down (fastpd), and full power-down (fullpd)). these devices can be programmed to automatically shut down at the end of a conversion or to operate with reduced power. when using the power-down modes, accessing the serial interface automatically powers up the devices, and the quick turn- on time allows them to be shut down between all conver- sions. the max1282/max1283 are available in 16-pin tssop packages. applications portable data logging data acquisition medical instruments battery-powered instruments pen digitizers process control features 4-channel single-ended or 2-channel pseudo-differential inputs internal multiplexer and track/hold single-supply operation +4.5v to +5.5v (max1282) +2.7v to +3.6v (max1283) internal +2.5v reference 400khz sampling rate (max1282) low power: 2.5ma (400ksps) 1.3ma (redp) 0.9ma (fastpd) 2? (fullpd) spi/qspi/microwire/tms320-compatible 4-wire serial interface software-configurable unipolar or bipolar inputs 16-pin tssop package ? 16 tssop 0? to +70? max1283 bcue ? 16 tssop -40? to +85? max1283beue ? 16 tssop -40? to +85? max1282beue inl (lsb) pin- package temp. range part ? 16 tssop 0? to +70? max1282 bcue
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ax1282 (v dd1 = v dd2 = +4.5v to +5.5v, com = gnd, f osc = 6.4mhz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd _ to gnd ........................................................... -0.3v to +6v v dd1 to v dd2 ....................................................... -0.3v to +0.3v ch0?h3, com to gnd .......................... -0.3v to (v dd _ +0.3v) ref, refadj to gnd ................................ -0.3v to v dd _ +0.3v) digital inputs to gnd .............................................. -0.3v to +6v digital outputs to gnd............................. -0.3v to (v dd _ +0.3v) digital output sink current .................................................25ma continuous power dissipation (t a = +70?) 16-pin tssop (derate 6.7mw/? above +70?) ........ 535mw operating temperature ranges max1282bcue/max1283bcue ....................... 0? to +70? max1282beue/max1283beue ..................... -40? to +85? storage temperature range ............................ -60? to +150? lead temperature (soldering, 10s) ................................ +300? sinad > 68db -3db point 200khz, v in = 2.5vp-p f in1 = 99khz, f in2 =102khz no missing codes over temperature up to the 5th harmonic conditions mhz 0.5 6.4 f sclk serial clock frequency ps <50 aperture jitter ns 10 aperture delay ns 400 t acq track/hold acquisition time ? 2.5 t conv conversion time (note 5) khz 350 full-linear bandwidth mhz 6 full-power bandwidth db -78 channel-to-channel crosstalk (note 4) db 76 imd intermodulation distortion db 80 sfdr spurious-free dynamic range db -81 thd total harmonic distortion bits 12 resolution db 70 sinad signal-to-noise plus distortion ratio lsb ?.2 channel-to-channel offset-error matching ppm/? ?.6 gain-error temperature coefficient ?.0 lsb ?.0 dnl differential nonlinearity lsb ?.0 offset error lsb ?.0 gain error (note 3) units min typ max symbol parameter % 40 60 duty cycle dynamic specifications (100khz sine-wave input, 2.5vp-p, 400ksps, 6.4mhz clock, bipolar input mode) dc accuracy (note 1) conversion rate lsb inl relative accuracy (note 2)
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference _______________________________________________________________________________________ 3 electrical characteristics?ax1282 (continued) (v dd1 = v dd2 = +4.5v to +5.5v, com = gnd, f osc = 6.4mhz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) conditions units min typ max symbol parameter to power down the internal reference for small adjustments, from 1.22v 0 to 1ma output load on/off leakage current, v com , v ch_ = 0 or v dd1 t a = +25? bipolar, v com or v ch_ = v ref /2, referenced to com or ch_ unipolar, v com = 0 v/v +2.05 buffer voltage gain v 1.4 v dd1 - 1.0 refadj buffer disable threshold mv ?00 refadj input range v 1.22 refadj output voltage ? 0.01 10 capacitive bypass at refadj ? 4.7 10 capacitive bypass at ref mv/ma 0.05 2.0 load regulation (note 7) ppm/? ?5 tc v ref ref output temperature coefficient ma 15 ref short-circuit current v 2.480 2.500 2.520 v ref ref output voltage pf 18 input capacitance ? ?.001 ? multiplexer leakage current ? ref /2 v v ref v ch_ input voltage range, single- ended and differential (note 6) v in = 0 or v dd2 in full power-down mode, f sclk = 0 v ref = 2.500v, f sclk = 0 v ref = 2.500v, f sclk = f max (note 8) pf c in input capacitance ? ? i in input leakage v 0.2 v hyst input hysteresis v 0.8 v inl input low voltage v 3.0 v inh input high voltage 5 320 ? 200 350 ref input current v 1.0 v dd1 + 50mv ref input voltage range i sink = 5ma v 0.4 v ol output voltage low 15 i source = 1ma v 4 v oh output voltage high cs = v dd2 ? ?0 i l three-state leakage current cs = v dd2 pf 15 c out three-state output capacitance analog inputs (ch3?h0, com) external reference (reference buffer disabled, reference applied to ref) internal reference digital inputs (din, sclk, cs , shdn ) digital outputs (dout, sstrb)
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 4 _______________________________________________________________________________________ v dd1 = v dd2 = 5.5v v dd1 = v dd2 = 5v ?0%, midscale input conditions ma 2.5 4.0 iv dd1 + iv dd2 supply current v 4.5 5.5 v dd1, v dd2 positive supply voltage (note 9) 1.3 2.0 0.9 1.5 ? 2.0 10 mv ?.5 ?.0 psr power-supply rejection units min typ max symbol parameter normal operating mode (note 10) reduced-power mode (note 11) fast power-down mode (note 11) full power-down mode (note 11) electrical characteristics?ax1282 (continued) (v dd1 = v dd2 = +4.5v to +5.5v, com = gnd, f osc = 6.4mhz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) electrical characteristics?ax1283 (v dd1 = v dd2 = +2.7v to +3.6v, com = gnd, f osc = 4.8mhz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) sinad > 68db -3db point f = 150khz, v in = 2.5vp-p f in1 = 73khz, f in2 = 77khz no missing codes over temperature up to the 5th harmonic conditions khz 250 full-linear bandwidth mhz 3 full-power bandwidth db -78 channel-to-channel crosstalk (note 4) db 76 imd intermodulation distortion db 72 sfdr spurious-free dynamic range db -70 thd total harmonic distortion bits 12 resolution db 70 sinad signal-to-noise plus distortion ratio lsb ?.2 channel-to-channel offset-error matching ppm/? ?.6 gain-error temperature coefficient ?.0 lsb ?.0 dnl differential nonlinearity lsb ?.0 offset error lsb ?.0 gain error (note 3) units min typ max symbol parameter power supply lsb inl relative accuracy (note 2) dc accuracy (note 1) dynamic specifications (100khz sine-wave input, 2.5vp-p, 400ksps, 6.4mhz clock, bipolar input mode)
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference _______________________________________________________________________________________ 5 electrical characteristics?ax1283 (continued) (v dd1 = v dd2 = +2.7v to +3.6v, com = gnd, f osc = 4.8mhz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) normal operating mode normal operating mode normal operating mode conditions mhz 0.5 4.8 f sclk serial clock frequency ps <50 aperture jitter ns 10 aperture delay ns 625 t acq track/hold acquisition time ? 3.3 t conv conversion time (note 5) units min typ max symbol parameter to power down the internal reference for small adjustments, from 1.22v 0 to 0.75ma output load on/off leakage current, v ch_ = 0 or v dd1 t a = +25? bipolar, v com or v ch_ = v ref /2, referenced to com or ch_ unipolar, v com = 0 v/v 2.05 buffer voltage gain v 1.4 v dd1 - 1.0 refadj buffer disable threshold mv ?00 refadj input range v 1.22 refadj output voltage ? 0.01 10 capacitive bypass at refadj ? 4.7 10 capacitive bypass at ref mv/ma 0.1 2.0 load regulation (note 7) ppm/? ?5 tc v ref ref output temperature coefficient ma 15 ref short-circuit current v 2.480 2.500 2.520 v ref ref output voltage pf 18 input capacitance ? ?.001 ? multiplexer leakage current ? ref /2 % 40 60 duty cycle v v ref v ch_ input voltage range, single ended and differential (note 6) v in = 0 or v dd2 in full power-down mode, f sclk = 0 v ref = 2.500v, f sclk = 0 v ref = 2.500v, f sclk = f max (note 8) pf 15 c in input capacitance ? ? i in input leakage v 0.2 v hyst input hysteresis v 0.8 v inl input low voltage v 2.0 v inh input high voltage 5 ref input current 320 ? 200 350 v 1.0 v dd1 + 50mv ref input voltage range v/v 2.05 buffer voltage gain conversion rate analog inputs (ch3?h0, com) internal reference external reference (reference buffer disabled, reference applied to ref) digital inputs (din, sclk, cs , shdn )
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 6 _______________________________________________________________________________________ v dd1 = v dd2 = 3.6v i source = 0.5ma v dd1 = v dd2 = 2.7v to 3.6v, midscale input conditions ma 2.5 3.5 iv dd1 + iv dd2 supply current v 2.7 3.6 v dd1, v dd2 v v dd2 - 0.5v v oh output voltage high positive supply voltage (note 9) 1.3 2.0 normal operating mode (note 10) reduced-power mode (note 11) 0.9 1.5 fast power-down mode (note 11) full power-down mode (note 11) ? 2.0 10 mv ?.5 ?.0 psr power-supply rejection units min typ max symbol parameter i sink = 5ma v 0.4 v ol output voltage low cs = v dd2 ? ?0 i l three-state leakage current cs = v dd2 pf 15 c out three-state output capacitance electrical characteristics?ax1283 (continued) (v dd1 = v dd2 = +2.7v to +3.6v, com = gnd, f osc = 4.8mhz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5v at ref, refadj = v dd1 , t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) timing characteristics?ax1282 (figures 1, 2, 5, 6; v dd1 = v dd2 = +4.5v to +5.5v, t a = t min to t max , unless otherwise noted.) c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf conditions ns 100 t csw cs pulse width high ns 65 t ste cs fall to sstrb enable ns 65 t doe cs fall to dout enable ns 10 65 t std cs rise to sstrb disable ns 10 65 t dod cs rise to dout disable ns 80 t stv sclk rise to sstrb valid ns 80 t dov sclk rise to dout valid ns 62 t cl sclk pulse width low ns 62 t ch ns 156 t cp sclk period sclk pulse width high ns 10 20 t sth sclk rise to sstrb hold ns 10 20 t doh sclk rise to dout hold ns 35 t cs1 cs rise to sclk rise ignore ns 35 t cso sclk rise to cs fall ignore ns 35 t ds din to sclk setup ns 0 t dh din to sclk hold ns 35 t css cs fall to sclk rise setup ns 0 t csh sclk rise to cs rise hold units min typ max symbol parameter digital outputs (dout, sstrb) power supply
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference _______________________________________________________________________________________ 7 timing characteristics?ax1283 (figures 1, 2, 5, 6; v dd1 = v dd2 = +2.7v to +3.6v, t a = t min to t max , unless otherwise noted.) c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf c load = 20pf conditions ns 100 t csw cs pulse width high ns 85 t ste cs fall to sstrb enable ns 85 t doe cs fall to dout enable ns 13 85 t std cs rise to sstrb disable ns 13 85 t dod cs rise to dout disable ns 100 t stv sclk rise to sstrb valid ns 100 t dov sclk rise to dout valid ns 83 t cl sclk pulse width low ns 83 t ch ns 208 t cp sclk period sclk pulse width high ns 13 20 t sth sclk rise to sstrb hold ns 13 20 t doh sclk rise to dout hold ns 45 t cs1 cs rise to sclk rise ignore ns 45 t cso sclk rise to cs fall ignore ns 45 t ds din to sclk setup ns 0 t dh din to sclk hold ns 45 t css cs fall to sclk rise setup ns 0 t csh sclk rise to cs rise hold units min typ max symbol parameter note 1: tested at v dd1 = v dd2 = v dd(min) , com = gnd, unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: offset nulled. note 4: ground the ?n?channel; sine wave is applied to all ?ff?channels. note 5: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: the common-mode range for the analog inputs (ch3?h0 and com) is from gnd to v dd1 . note 7: external load should not change during conversion for specified accuracy. note 8: adc performance is limited by the converter? noise floor, typically 300?p-p. an external reference below 2.5v compro- mises the performance of the adc. note 9: electrical characteristics are guaranteed from v dd1(min) = v dd2(min) to v dd1(max) = v dd2(min) . for operations beyond this range, see typical operating characteristics . for guaranteed specifications beyond the limits, contact the factory. note 10: ain = midscale, unipolar mode. max1282 tested with 20pf on dout, 20pf on sstrb, and f sclk = 6.4mhz, 0 to 5v. max1283 tested with same loads, f sclk = 4.8mhz, 0 to 3v. note 11: sclk = din = gnd, cs = v dd1 .
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 8 _______________________________________________________________________________________ typical operating characteristics (max1282: v dd1 = v dd2 = 5.0v, f sclk = 6.4mhz; max1283: v dd1 = v dd2 = 3.0v, f sclk = 4.8mhz; c load = 20pf, 4.7? capacitor at ref, 0.01? capacitor at refadj, t a = +25?, unless otherwise noted.) 0 1500 2000 500 1000 2500 3000 3500 4000 4500 integral nonlinearity vs. digital output code max1280/1-01 digital output code inl (lsb) -0.2 0 0.2 0.4 -0.3 -0.4 -0.1 0.1 0.3 -0.5 -0.4 -0.2 0 0.3 0.4 0.5 0 1000 500 1500 2000 2500 3000 3500 4000 4500 differential nonlinearity vs. digital output code max1280/1-02 dnl (lsb) digital output code 0.2 0.1 -0.1 -0.3 3.5 3.0 2.5 2.0 1.5 2.5 4.0 3.0 3.5 4.5 5.0 5.5 supply current vs. supply voltage (converting) max1282/3-03 supply voltage (v) supply current (ma) 2.0 2.4 2.2 2.8 2.6 3.0 3.2 -40 20 40 -20 0 60 80 100 supply current vs. temperature max1282/3-04 temperature ( c) supply current (ma) max1283 max1282 normal operation (pd1 = pd0 = 1) redp (pd1 = 1, pd0 = 0) fastdp (pd1 = 0, pd0 = 1) 0 0.5 1.5 1.0 2.0 2.5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 supply current vs. supply voltage (static) max1282/3-05 supply voltage (v) supply current (ma) 0 0.5 1.5 1.0 2.0 2.5 -40 0 -20 20 40 60 80 100 supply current vs. temperature (static) max1282/3-06 temperature ( c) supply current (ma) max1282 (pd1 = 1, pd0 = 1) max1282 (pd1 = 1, pd0 = 0) max1282 (pd1 = 0, pd0 = 1) max1283 (pd1 = 1, pd0 = 1) max1283 (pd1 = 1, pd0 = 0) max1283 (pd1 = 0, pd0 = 1) 0 1 3 2 4 5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 shutdown current vs. supply voltage max1282/3-07 supply voltage (v) supply current ( a) (pd1 = pd0 = 0) 0 0.5 1.5 1.0 2.0 2.5 -40 0 -20 20 40 60 80 100 shutdown supply current vs. temperature max1282/3-08 temperature ( c) supply current (?) max1283 max1282 (pd1 = pd0 = 0) 2.4995 2.4997 2.5001 2.4999 2.5003 2.5005 2.5 3.5 3.0 4.0 4.5 5.0 5.5 reference voltage vs. supply voltage max1282/3-09 supply voltage (v) reference voltage (v)
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference _______________________________________________________________________________________ 9 2.4988 2.4992 2.4990 2.4996 2.4994 2.5000 2.4998 2.5002 -40 0 20 -20 40 60 80 100 reference voltage vs. temperature max1282/3-10 temperature ( c) reference voltage (v) max1283 max1282 -2.0 -1.0 -1.5 0.5 -0.5 0 1.5 1.0 2.0 offset error vs. supply voltage max1282/3-11 supply voltage (v) offset error (lsb) 2.5 3.0 4.5 3.5 4.0 5.0 5.5 -2.5 -1.5 -2.0 -0.5 -1.0 0 0.5 -40 10 -15 35 60 85 offset error vs. temperature max1282/3-12 temperature ( c) offset error (lsb) -1.0 0 0.4 0.2 -0.4 -0.6 -0.8 -0.2 0.6 0.8 1.0 2.5 3.0 4.5 3.5 4.0 5.0 5.5 gain error vs. supply voltage max1282/3-13 supply voltage (v) gain error (lsb) -2.0 -1.5 -0.5 -1.0 0 0.5 gain error vs. temperature max1282/3-14 temperature ( c) gain error (lsb) -40 10 -15 35 60 85 typical operating characteristics (continued) (max1282: v dd1 = v dd2 = 5.0v, f sclk = 6.4mhz; max1283: v dd1 = v dd2 = 3.0v, f sclk = 4.8mhz; c load = 20pf, 4.7? capacitor at ref, 0.01? capacitor at refadj, t a = +25?, unless otherwise noted.)
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 10 ______________________________________________________________________________________ pin description positive supply voltage v dd2 16 input to the reference-buffer amplifier. to disable the reference-buffer amplifier, connect refadj to v dd1 . refadj 9 serial strobe output. sstrb pulses high for one clock period before the msb decision. high impedance when cs is high. sstrb 12 serial-data input. data is clocked in at sclk? rising edge. din 13 active-low chip select. data will not be clocked into din unless cs is low. when cs is high, dout and sstrb are high impedance. cs 14 serial-clock input. clocks data in and out of serial interface and sets the conversion speed. (duty cycle must be 40% to 60%.) sclk 15 reference-buffer output/adc reference input. reference voltage for analog-to-digital conversion. in internal reference mode, the reference buffer provides a 2.500v nominal output, externally adjustable at refadj. in external reference mode, disable the internal buffer by pulling refadj to v dd1 . ref 8 ground gnd 10 serial-data output. data is clocked out at sclk? rising edge. high impedance when cs is high. dout 11 active-low shutdown input. pulling shdn low shuts down the device, reducing supply current to 2? (typ). shdn 7 ground reference for analog inputs. com sets zero-code voltage in single-ended mode. must be stable to ?.5lsb. com 6 pin positive supply voltage v dd1 1 function name v dd2 3k gnd dout c load 50pf c load 50pf gnd 3k dout a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol v dd2 3k gnd dout c load 70pf c load 20pf gnd 3k dout a) v oh to high-z b) v ol to high-z figure 1. load circuits for enable time figure 2. load circuits for disable time sampling analog inputs ch0?h3 2?
detailed description the max1282/max1283 adcs use a successive- approximation conversion technique and input t/h cir- cuitry to convert an analog signal to a 12-bit digital out- put. a flexible serial interface provides easy interface to microprocessors (?s). figure 3 shows a functional dia- gram of the max1282/max1283. pseudo-differential input the equivalent circuit of figure 4 shows the max1282/ max1283? input architecture, which is composed of a t/h, input multiplexer, input comparator, switched- capacitor dac, and reference. in single-ended mode, the positive input (in+) is con- nected to the selected input channel and the negative input (in-) is set to com. in differential mode, in+ and in- are selected from the following pairs: ch0/ch1 and ch2/ch3. configure the channels according to tables 1 and 2. the max1282/max1283 input configuration is pseudo- differential because only the signal at in+ is sampled. the return side (in-) is connected to the sampling capacitor while converting and must remain stable within ?.5lsb (?.1lsb for best results) with respect to gnd during a conversion. if a varying signal is applied to the selected in-, its amplitude and frequency must be limited to maintain accuracy. the following equations express the relation- ship between the maximum signal amplitude and its frequency to maintain ?.5lsb accuracy. assuming a sinusoidal signal at in-, the input voltage is determined by: the maximum voltage variation is determined by: a 0.65vp-p, 60hz signal at in- will generate a ?.5lsb error when using a +2.5v reference voltage and a 2.5? conversion time (15 / f sclk ). when a dc refer- ence voltage is used at in-, connect a 0.1? capacitor to gnd to minimize noise at the input. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans three sclk cycles and ends on the falling sclk edge after the input control word? last bit has been entered. at the end of the acquisition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conver- sion interval begins with the input multiplexer switching c hold from in+ to in-. this unbalances node zero at the comparator? input. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to v dd1 / 2 within the limits of 12-bit resolu- tion. this action is equivalent to transferring a 12pf ? (v in + - v in -) charge from c hold to the binary- weighted capacitive dac, which in turn forms a digital representation of the analog input signal. max d dt v2f 1lsb t v 2t conv ref 12 conv in in ? =? = () max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference ______________________________________________________________________________________ 11 input shift register control logic int clock output shift register +1.22v reference t/h analog input mux 12-bit sar adc in dout sstrb v dd1 v dd2 gnd sclk din com refadj ref out ref clock +2.500v 17k 7 8 9 6 11 12 13 14 15 ch1 3 ch2 4 ch3 5 ch0 2 max1282 max1283 cs shdn 1 16 10 2.05 a figure 3. functional diagram c hold 12pf r in 800 ? hold input mux c switch * *includes all input parasitics single-ended mode: in+ = ch0?h3, in- = com. pseudo-differential mode: in+ and in- selected from pairs of ch0/ch1 and ch2/ch3. at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. ch0 ref gnd ch1 ch2 ch3 com zero v dd1 /2 comparator capacitive dac 6pf track figure 4. equivalent input circuit ? in in v sin(2 ft) ?= ? ()
table 1. channel selection in single-ended mode (sgl/ dif = 1) table 2. channel selection in pseudo-differential mode (sgl/ dif = 0) max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 12 ______________________________________________________________________________________ track/hold the t/h enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. it enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. if the converter is set up for single-ended inputs, in- is connected to com and the converter samples the ??input. if the converter is set up for dif- ferential inputs, the difference of [( in+) - (in-) ] is con- verted. at the end of the conversion, the positive input connects back to in+ and c hold charges to the input signal. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal and the minimum time needed for the signal to be acquired. it is calculated by the following equa- tion: t acq = 9 ? (r s + r in ) ? 18pf where r in = 800 ? and r s = the source impedance of the input signal; t acq is never less than 400ns (max1282) or 625ns (max1283). note that source impedances below 2k ? do not significantly affect the adc? ac performance. input bandwidth the adc? input tracking circuitry has a 6mhz (max1282) or 3mhz (max1283) small-signal band- width, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using under- sampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti- alias filtering is recommended. analog input protection internal protection diodes, which clamp the analog input to v dd1 and gnd, allow the channel input pins to swing from gnd - 0.3v to v dd1 + 0.3v without damage. however, for accurate conversions near full scale, the inputs must not exceed v dd1 by more than 50mv or be lower than gnd by 50mv. if the analog input exceeds 50mv beyond the sup- plies, do not allow the input current to exceed 2ma. starting a conversion start a conversion by clocking a control byte into din. with cs low, each rising edge on sclk clocks a bit from din into the max1282/max1283? internal shift register. after cs falls, the first arriving logic ??bit defines the control byte? msb. until this first ?tart?bit arrives, any number of logic ??bits can be clocked into din with no effect. table 3 shows the control-byte format. the max1282/max1283 are compatible with spi/ qspi/microwire devices. for spi, select the correct clock polarity and sampling edge in the spi control reg- isters: set cpol = 0 and cpha = 0. microwire, spi, and qspi all transmit a byte and receive a byte at the same time. using the typical operating circuit , the sim- plest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the sel2 sel1 sel0 ch0 ch1 ch2 ch3 com 00 1+ 10 1 + 01 0 + 11 0 + sel2 sel1 sel0 ch0 ch1 ch2 ch3 00 1+ 01 0 + 10 1+ 11 0 +
conversion result). (see figure 16 for max1282/ max1283 qspi connections.) simple software interface make sure the cpu? serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 500khz to 6.4mhz (max1282) or 4.8mhz (max1283). 1) set up the control byte and call it tb1. tb1 should be in the format: 1xxxxxxx binary, where the xs denote the particular channel, selected conversion mode, and power mode. 2) use a general-purpose i/o line on the cpu to pull cs low. 3) transmit tb1 and, simultaneously, receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb3. 6) pull cs high. figure 5 shows the timing for this sequence. bytes rb2 and rb3 contain the result of the conversion, padded with three leading zeros, and one trailing zero. the total conversion time is a function of the serial-clock fre- quency and the amount of idle time between 8-bit transfers. to avoid excessive t/h droop, make sure the total conversion time does not exceed 120?. digital output in unipolar input mode, the output is straight binary (figure 13). for bipolar input mode, the output is two? complement (figure 14). data is clocked out on the ris- ing edge of sclk in msb-first format. serial clock the external clock not only shifts data in and out, but it also drives the analog-to-digital conversion steps. sstrb pulses high for one clock period after the last bit of the control byte. successive-approximation bit deci- sions are made and appear at dout on each of the next 12 sclk rising edges, msb first (figure 5). sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb out- puts a logic low. figure 6 shows the detailed serial-inter- face timings. the conversion must complete in 120? or less, or droop on the sample-and-hold capacitors may degrade conversion results. data framing the falling edge of cs does not start a conversion. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. a conversion starts on sclk? falling edge, after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as follows: the first high bit clocked into din with cs low any time the converter is idle, e.g., after v dd1 and v dd2 are applied. or the first high bit clocked into din after b6 of a con- version in progress is clocked onto the dout pin (figure 7). once a start bit has been recognized, the current conver- sion may only be terminated by pulling shdn low. the fastest the max1282/max1283 can run with cs held low between conversions is 16 clocks per conversion. figure 7 shows the serial-interface timing necessary to perform a conversion every 16 sclk cycles. if cs is tied low and sclk is continuous, guarantee a start bit by first clocking in 16 zeros. ___________applications information power-on reset when power is first applied, and if shdn is not pulled low, internal power-on reset circuitry activates the max1282/max1283 in normal operating mode, ready to convert with sstrb = low. after the power supplies sta- bilize, the internal reset time is 10?, and no conver- sions should be performed during this phase. if cs is low, the first logic 1 on din is interpreted as a start bit. until a conversion takes place, dout shifts out zeros. additionally, wait for the reference to stabilize when using the internal reference. power modes save power by placing the converter in one of two low- current operating modes or in full power-down between conversions. select the power-down mode through bit 1 and bit 0 of the din control byte (tables 3 and 4), or force the converter into hardware shutdown by driving shdn to gnd. the software power-down modes take effect after the conversion is completed; shdn overrides any software power mode and immediately stops any conversion in progress. in software power-down mode, the serial interface remains active while waiting for a new control byte to start conversion and switch to full-power mode. max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference ______________________________________________________________________________________ 13
max1282/max1283 once conversion is completed, the device goes into the programmed power mode until a new control byte is written. the power-up delay is dependent on the power-down state. software low-power modes will be able to start conversion immediately when running at decreased clock rates (see power-down sequencing ). upon power-on reset, when exiting software full power-down mode, or when exiting hardware shutdown, the device goes immediately into full-power mode and is ready to convert after 2? when using an external reference. when using the internal reference, wait for the typical power-up delay from a full power-down (software or hardware) as shown in figure 8. software power-down software power-down is activated using bits pd1 and pd0 of the control byte. when software power-down is asserted, the adc completes the conversion in 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 14 ______________________________________________________________________________________ bit name description 7(msb) start the first logic 1 bit after cs goes low defines the beginning of the control byte. 6 sel2 these three bits select which of the eight channels are used for the conversion (tables 1 and 2). 5 sel1 4 sel0 3 uni/bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0 to v ref can be converted; in bipolar mode, the differential signal can range from -v ref /2 to +v ref /2. 2 sgl/dif 1 = single ended, 0 = pseudo-differential. selects single-ended or pseudo-differential conver- sions. in single-ended mode, input signal voltages are referred to com. in pseudo-differential mode, the voltage difference between two channels is measured (tables 1 and 2). 1 pd1 select operating mode. 0(lsb) pd0 pd1 pd0 mode 0 0 full power-down 0 1 fast power-down 1 0 reduced power 1 1 normal operation table 3. control-byte format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 pd1/pd0 mode converting (ma) after conversion input comparator reference 00 full power-down (fullpd) 2.5 2? off off 01 fast power-down (fastpd) 2.5 0.9ma reduced power on 10 reduced-power mode (redp) 2.5 1.3ma reduced power on 11 normal operating 2.5 2.0ma full power on circuit sections* total supply current table 4. software-controlled power modes *circuit operation between conversions; during conversion all circuits are fully powered up.
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference ______________________________________________________________________________________ 15 progress and powers down into the specified low-qui- escent-current state (2?, 0.9ma, or 1.3ma). the first logic 1 on din is interpreted as a start bit and puts the max1282/max1283 into its full-power mode. following the start bit, the data input word or control byte also determines the next power-down state. for example, if the din word contains pd1 = 0 and pd0 = 1, a 0.9ma power-down resumes after one conversion. table 4 details the four power modes with the corre- sponding supply current and operating sections. hardware power-down pulling shdn low places the converter in hardware power-down. unlike software power-down mode, the conversion is not completed; it stops coincidentally with shdn being brought low. when returning to normal operation?rom shdn , with an external reference?he max1282/max1283 can be considered fully powered up within 2? of actively pulling shdn high. when using the internal reference, the conversion should be initiated only when the reference has settled; its recov- ery time is dependent on the external bypass capaci- tors and the time between conversions. power-down sequencing the max1282/max1283 auto power-down modes can save considerable power when operating at less than maximum sample rates. figures 9 and 10 show the average supply current as a function of the sampling rate. the following sections discuss the various power- down sequences. other combinations of clock rates and power-down modes may attain the lowest power consumption in other applications. using full power-down mode full power-down mode (fullpd) achieves the lowest power consumption, up to 1000 conversions per chan- nel per second. figure 9a shows the max1283? power consumption for one- or four-channel conversions utiliz- ing full power-down mode (pd1 = pd0 = 0), with the internal reference and conversion controlled at the maximum clock speed. a 0.01? bypass capacitor at refadj forms an rc filter with the internal 17k ? refer- ence resistor, with a 170? time constant. to achieve full 12-bit accuracy, nine time constants or 1.5ms are required after power-up if the bypass capacitor is fully discharged between conversions. waiting this 1.5ms duration in fast power-down (fastpd) or reduced- power (redp) mode instead of in full power-up can fur- ther reduce power consumption. this is achieved by using the sequence shown in figure 11a. figure 9b shows the max1283? power consumption for one- or four-channel conversions utilizing fullpd mode (pd1 = pd0 = 0), with an external reference and conversion controlled at the maximum clock speed. one dummy conversion to power up the device is needed, but no waiting time is necessary to start the second conversion, thereby achieving lower power consumption as low as half the full sampling rate. 400ns (clk = 6.4mhz) idle cs sclk din sstrb dout a/d state t acq idle conversion rb3 rb2 rb1 sel 2 1 start 4 891216 2024 sel 1 sel 0 uni/ bip sgl/ dif pd2 pd2 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 figure 5. single-conversion timing
max1282/max1283 using fast power-down and reduced-power modes fastpd and redp modes achieve the lowest power consumption at speeds close to the maximum sampling rate. figure 10 shows the max1283? power consumption in fastpd mode (pd1 = 0, pd0 = 1), redp mode (pd1 = 1, pd0 = 0), and, for comparison, normal operating mode (pd1 = 1, pd0 = 1). the figure shows power consumption using the specified power- down mode, with the internal reference and conversion controlled at the maximum clock speed. the clock speed in fastpd or redp should be limited to 4.8mhz for the max1282/max1283. fullpd mode may provide increased power savings in applications where the max1282/max1283 are inactive for long periods of time, but intermittent bursts of high-speed conversions are required. figure 11b shows fastpd and redp timing. internal and external references the max1282/max1283 can be used with an internal or external reference voltage. an external reference can be connected directly at ref or at the refadj pin. an internal buffer is designed to provide 2.5v at ref for the max1282/max1283. the internally trimmed 1.22v reference is buffered with a 2.05 gain. internal reference the max1282/max1283? full-scale range with the inter- nal reference is 2.5v with unipolar inputs and ?.25v with bipolar inputs. the internal reference voltage is adjustable by ?00mv with the circuit in figure 12. external reference the max1282/max1283? external reference can be placed at the input (refadj) or the output (ref) of the internal reference-buffer amplifier. the refadj input impedance is typically 17k ? . at ref, the dc input resistance is a minimum of 18k ? . during conversion, an external reference at ref must deliver up to 350? dc load current and have 10 ? or less output impedance. if the reference has a higher output impedance or is noisy, bypass it close to the ref pin with a 4.7? capacitor. 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 16 ______________________________________________________________________________________ sclk din dout sstrb t css t ch t cso t cl t dh t doe t ds t ste t csw t cp t csh t cs1 t std t dod t dov t doh t stv t sth cs #10 figure 6. detailed serial-interface timing unipolar mode bipolar mode full scale zero scale positive zero negative full scale scale full scale table 5. full scale and zero scale v ref + v com v ref / 2 + v com v ref / 2 + v com v com v com
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference ______________________________________________________________________________________ 17 sclk 11 1 5 8858 12 12 12 16 16 1 5 16 b6 b11 b0 b6 b11 b0 din sstrb dout cs control byte 0 sss control byte 1 conversion result 1 conversion result 0 control byte 2 s etc b6 b11 figure 7. continuous 16-clock/conversion timing 0 0.50 0.25 1.00 0.75 1.25 1.50 0.0001 0.01 0.001 0.1 1 10 time in shutdown (s) reference power-up delay (ms) max1283, v dd1 = v dd2 = 3.0v c load = 20pf code = 101010000000 1k 100 10 1 0.1 10 1 100 1k 10k sampling rate (sps) supply current ( a) 4 channels 1 channel 10k 1k 10 100 1 1 100 10 1k 10k 100k sampling rate (sps) supply current ( a) max1283, v dd1 = v dd 2 = 3.0v c load = 20pf code = 101010000000 4 channels 1 channel figure 8. reference power-up delay vs. time in shutdown figure 9a. average supply current vs. conversion rate with internal reference in fullpd figure 9b. average supply current vs. conversion rate with external reference in fullpd 2.5 2.0 1.0 1.5 0.5 0 150 250 100 50 200 300 350 sampling rate (sps) supply current (ma) max1283, v dd1 = v dd2 = 3.0v c load = 20pf code = 101010000000 redp fastpd normal operation figure 10. average supply current vs. sampling rate (in fastpd, redp, and normal operation)
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 18 ______________________________________________________________________________________ figure 11a. full power-down timing re fadj 1.22v 1.22v 0v 2.5ma 2.5ma 1.3ma or 0.9ma din i vdd1 + i vdd2 ref fullpd redp wait 2ms (10 x rc) fullpd 1 0 0 11 = rc = 17k ? x 0.01 f dummy conversion 1 1 0 0 0 2.5v 2.5ma 0ma 0ma 2.5v 0v figure 11b. fastpd and redp timing 2.5v (always on) 2.5ma 2.5ma din iv dd1 + iv dd2 ref redp redp fastpd 1 1 0 11 1 0 0 1 2.5ma 0.9ma 0.9ma 1.3ma to use the direct ref input, disable the internal buffer by connecting refadj to v dd1 . using the refadj input makes buffering the external reference unnecessary. transfer function table 5 shows the full-scale voltage ranges for unipolar and bipolar modes. figure 13 depicts the nominal, unipolar input/output (i/o) transfer function, and figure 14 shows the bipolar i/o transfer function. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1lsb = 0.61mv (2.500v / 4096) for unipo- lar operation, and 1lsb = 0.61mv [(2.500v / 2) / 4096] for bipolar operation. layout, grounding, and bypassing for best performance, use pc boards; wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digital (espe- cially clock) lines parallel to one another, or digital lines underneath the adc package. figure 15 shows the recommended system ground connections. establish a single-point analog ground (star ground point) at gnd. connect all other analog grounds to the star ground. connect the digital system ground to this ground only at this point. for lowest- noise operation, the ground return to the star ground? power supply should be low impedance and as short as possible. high-frequency noise in the v dd1 power supply may affect the high-speed comparator in the adc. bypass the supply to the star ground with 0.1? and 10? capacitors close to v dd1 of the max1282/max1283. minimize capacitor lead lengths for best supply-noise rejection. if the power supply is very noisy, a 10 ? resis- tor can be connected as a lowpass filter (figure 15). high-speed digital interfacing with qspi the m ax1282/max1283 can interface with qspi using the circuit in figure 16 (cpol = 0, cpha = 0). this qspi circuit can be programmed to do a conversion on each of the four channels. the result is stored in memory without taxing the cpu, since qspi incorporates its own microsequencer.
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference ______________________________________________________________________________________ 19 tms320lc3x interface figure 17 shows an application circuit to interface the max1282/max1283 to the tms320 in external clock mode. the timing diagram for this interface circuit is shown in figure 18. use the following steps to initiate a conversion in the max1282/max1283 and to read the results: 1) the tms320 should be configured with clkx (trans- mit clock) as an active-high output clock and clkr (tms320 receive clock) as an active-high input clock. clkx and clkr on the tms320 are connected to the max1282/max1283? sclk input. 2) the max1282/max1283? cs pin is driven low by the tms320? xf_ i/o port to enable data to be clocked into the max1282/max1283? din pin. 3) an 8-bit word (1xxxxx11) should be written to the max1282/max1283 to initiate a conversion and place the device into normal operating mode. see table 3 to select the proper xxxxx bit values for your specific application. 4) the max1282/max1283? sstrb output is moni- tored through the tms320? fsr input. a falling edge on the sstrb output indicates that the conver- sion is in progress and data is ready to be received from the device. 5) the tms320 reads in 1 data bit on each of the next 16 rising edges of sclk. these data bits represent the 12-bit conversion result followed by 4 trailing bits, which should be ignored. 6) pull cs high to disable the max1282/max1283 until the next conversion is initiated. +3.3v 510k 24k 100k 0.047 f 12 refadj max1282 max1283 figure 12. max1282/max1283 reference-adjust circuit output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 (com) fs fs - 3/2lsb fs = v ref + v com zs = v com input voltage (lsb) 1lsb = v ref 4096 figure 13. unipolar transfer function, full scale (fs) = v ref + v com , zero scale (zs) = v com 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs com* input voltage (lsb) output code zs = v com +fs - 1lsb *v com v ref / 2 + v com fs = v ref 2 -fs = + v com -v ref 2 1lsb = v ref 4096 figure 14. bipolar transfer function, full scale (fs) = v ref / 2 + v com , zero scale (zs) = v com
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 20 ______________________________________________________________________________________ definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values from a straight line on an actual transfer function. this straight line can be a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the max1282/max1283 are measured using the best straight-line fit method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. aperture width aperture width (t aw ) is the time the t/h circuit requires to disconnect the hold capacitor from the input circuit (for instance, to turn off the sampling bridge, and put the t/h unit in hold mode). aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (resid- ual error). the ideal, theoretical minimum analog-to-dig- ital noise is caused only by quantization error and results directly from the adc? resolution (n bits): snr = (6.02 ? n + 1.76)db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is the ratio of the fundamental input frequency? rms amplitude to rms equivalent of all other adc out- put signals: sinad (db) = 20 ? log (signal rms / noise rms ) effective number of bits (enob) enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists only of quantization noise. with an input range equal to the adc? full-scale range, calcu- late enob as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of the input signal? first five harmonics to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the funda- mental (maximum signal component) to the rms value of the next-largest distortion component. thd 20 log vvvvv v 2 2 3 2 4 2 4 2 5 2 1 = ++++ ? ? ? ? ? ? +3v +3v supplies dgnd +3v v dd2 com gnd v dd1 digital circuitry max1282 max1283 *r = 10 ? *optional gnd figure 15. power-supply grounding connection
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference ______________________________________________________________________________________ 21 mc683xx (power supplies) sck pcs0 mosi miso 0.1 f 10 f (gnd) 0.01 f 4.7 f analog inputs +5v or +3v +5v or +3v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 max1282 max1283 v dd2 sclk csb din sstrb dout gnd refadj v dd1 ch0 ch1 com ch2 ch3 shdn ref 10 f 0.1 f v dd1 figure 16. qspi connections xf clkx clkr dx dr fsr cs sclk din dout sstrb tms320lc3x max1282 max1283 figure 17. max1282/max1283-to-tms320 serial interface
300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference 22 ______________________________________________________________________________________ sclk din dout sstrb sel2 start sel1 sel0 pd1 pd0 cs uni/bip sgi/dif b10 b1 msb b0 high impedance high impedance figure 18. max1282/max1283-to-tms320 serial interface typical operating circuit v dd i/o sck (sk) mosi (so) miso (si) v ss sstrb dout din sclk com gnd v dd2 v dd1 ch3 4.7 f 0.1 f ch0 0 to +2.5v analog inputs max1282 max1283 cpu shdn cs +5v or +3v ref 0.01 f refadj chip information transistor count: 4286 process: bicmos max1282/max1283
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference ______________________________________________________________________________________ 23 ________________________________________________________package information tssop.eps note: the max1282/max1283 do not have an exposed die pad.
max1282/max1283 300ksps/400ksps, single-supply, 4-channel, serial 12-bit adcs with internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2000 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

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